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  • Call for Papers (Special Issue on Reconfigurable Computing for Energy Efficient AI Microchip Technologies)

    CALL FOR PAPERS

    Many Artificial Intelligence (AI) processing tasks, especially those related to deep neural networks, are both computation and memory intensive. Yet the traditional computing platforms such as CPU are increasingly facing difficulties in dealing with those massive workloads. Reconfigurable Computing (RC) features the ability to perform computations in hardware to increase execution capabilities, and at the same time retain much of the flexibility of a software solution. The microchip design based on the Reconfigurable Computing models and principles has emerged as an effective means to ensure that the AI applications can be accelerated to not only meet the performance and throughput targets but also power and energy efficiency requirements.


    In this special issue of the Journal of Semiconductors, we call for the most advanced research results on various AI microchip design technologies based on the Reconfigurable Computing architectures. We invite submissions of original research articles/communications and comprehensive reviews to this special issue. Topics of interest include (but are not limited to) the following:

    l  Software/Compilers/Tools for mapping deep neural networks to RC-based accelerators 
    l Micro-architecture designs of hardware accelerators for RC
    l Deep neural network acceleration on existing accelerators such as FPGA, CGRA, or PSoC 
    l RC-based acceleration for edge computing and IoT; RC-based acceleration for cloud computing
    l  Hardware friendly deep neural network modeling, optimization, quantization, and compression Comparison studies of different RC-based acceleration architectures (FPGAs, CGRAs, PSoCs, etc.)
    l Reconfigurable approaches applied to analog or mixed signal integrated circuits and signal processing
    l Reconfigurable design for intelligent MEMS sensory systems
    l Survey and tutorial studies of AI microchip design technologies based on the Reconfigurable Computing architectures.


    Prof. Shaojun Wei of Tsinghua University will preface this special issue in the Comments and Opinions.


    GUEST EDITORS:

    Prof. Haigang Yang, Institute of Electronics, Chinese Academy of Sciences, 100190, Beijing, China. 
    E-mail: yanghg@mail.ie.ac.cn
    Web: http://people.ucas.edu.cn/~yanghg
    Prof. Yajun Ha, School of Information Science and Technology, ShanghaiTech University, 201210, Shanghai, China.  
    E-mail: hayj@shanghaitech.edu.cn
    Web: http://old.shanghaitech.edu.cn/faculty/sist/people/1245.html
    Prof. Lingli Wang, State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, 200433, Shanghai, China. 
    E-mail:  llwang@fudan.edu.cn
    Web: https://sme.fudan.edu.cn/info/detail?id=178
    Prof. Wei Zhang, Reconfigurable Computing Systems Lab, Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology, Kowloon, Hong Kong, China 
    E-mail: wei.zhang@ust.hk
    Web: http://www.ece.ust.hk/~eeweiz/
    Prof. Yingyan Lin, Efficient and Intelligent Computing (EIC) Lab, Department of Electrical and Computer Engineering, Rice University, Houston, TX 77005-1892, USA 
    E-mail: yingyan.lin@rice.edu
    Web: http://yl150.web.rice.edu/eicl_index.html

    Manuscript Submission:

    Manuscripts must be prepared according to Journal’s guidelines, available athttp://iopscience.iop.org/journal/1674-4926 .

    Submit your manuscripts directly to the listing guest editors via the e-mail addresses above. Or directly submit via the online submission address at https://mc03.manuscriptcentral.com/jos-iop 

    Please notify well in advance for your intension to submit a research paper.


    Key timetable dates:

    Manuscript due: August 31, 2019 
    Authors’ notification: September 30, 2019 
    Publication date: Publication date: October 31, 2019

    2019-01-21

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